37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
Finish these thigns before merging teh branch
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* zig targets
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- use non-reflection based cpu detection?
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* finish refactoring target/arch/*
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const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
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&std.target.riscv.feature_a,
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&std.target.riscv.feature_c,
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&std.target.riscv.feature_d,
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&std.target.riscv.feature_f,
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&std.target.riscv.feature_m,
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&std.target.riscv.feature_relax,
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};
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const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
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&std.target.riscv.feature_bit64,
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&std.target.riscv.feature_a,
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&std.target.riscv.feature_c,
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&std.target.riscv.feature_d,
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&std.target.riscv.feature_f,
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&std.target.riscv.feature_m,
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&std.target.riscv.feature_relax,
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};
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// Same as above but without sse.
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const i386_default_features_freestanding: []*const std.target.Feature = &[_]*const std.target.Feature{
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&std.target.x86.feature_cmov,
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&std.target.x86.feature_cx8,
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&std.target.x86.feature_fxsr,
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&std.target.x86.feature_mmx,
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&std.target.x86.feature_nopl,
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&std.target.x86.feature_slowUnalignedMem16,
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&std.target.x86.feature_x87,
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};
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