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https://github.com/raspberrypi/pico-sdk.git
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replace use of raw registers with new NVIC struct
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777cd52e21
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@ -9,6 +9,7 @@
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#include "hardware/platform_defs.h"
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#include "hardware/structs/scb.h"
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#include "hardware/claim.h"
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#include "hardware/structs/nvic.h"
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#include "pico/mutex.h"
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#include "pico/assert.h"
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@ -53,23 +54,23 @@ void irq_set_enabled(uint num, bool enabled) {
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bool irq_is_enabled(uint num) {
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check_irq_param(num);
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return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)));
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return 0 != (nvic_hw->iser & (1u << num));
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}
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void irq_set_mask_enabled(uint32_t mask, bool enabled) {
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if (enabled) {
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// Clear pending before enable
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// (if IRQ is actually asserted, it will immediately re-pend)
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask;
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask;
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nvic_hw->icpr = mask;
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nvic_hw->iser = mask;
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} else {
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask;
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nvic_hw->icer = mask;
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}
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}
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void irq_set_pending(uint num) {
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check_irq_param(num);
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*((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;
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nvic_hw->ispr = 1u << num;
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}
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#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
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@ -378,7 +379,7 @@ void irq_set_priority(uint num, uint8_t hardware_priority) {
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check_irq_param(num);
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// note that only 32 bit writes are supported
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io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
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io_rw_32 *p = &nvic_hw->ipr[num>>2];
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*p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));
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}
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@ -386,7 +387,7 @@ uint irq_get_priority(uint num) {
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check_irq_param(num);
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// note that only 32 bit reads are supported
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io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
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io_rw_32 *p = &nvic_hw->ipr[num>>2];
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return (uint8_t)(*p >> (8 * (num & 3u)));
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}
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@ -428,7 +429,7 @@ void irq_init_priorities() {
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#if PICO_DEFAULT_IRQ_PRIORITY != 0
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static_assert(!(NUM_IRQS & 3), "");
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uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u;
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io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET);
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io_rw_32 * p = &nvic_hw->ipr[0];
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for (uint i = 0; i < NUM_IRQS / 4; i++) {
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*p++ = prio4;
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}
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